|
| #define | TPI_ACPR_SWOSCALER_Pos 0U |
| |
| #define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
| |
| #define | TPI_PSCR_PSCount_Pos 0U |
| |
| #define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
| |
| #define | TPI_LSR_nTT_Pos 1U |
| |
| #define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
| |
| #define | TPI_LSR_SLK_Pos 1U |
| |
| #define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
| |
| #define | TPI_LSR_SLI_Pos 0U |
| |
| #define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
| |
| #define | TPI_ACPR_SWOSCALER_Pos 0U |
| |
| #define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
| |
| #define | TPI_PSCR_PSCount_Pos 0U |
| |
| #define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
| |
| #define | TPI_LSR_nTT_Pos 1U |
| |
| #define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
| |
| #define | TPI_LSR_SLK_Pos 1U |
| |
| #define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
| |
| #define | TPI_LSR_SLI_Pos 0U |
| |
| #define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
| |
| #define | TPI_ACPR_SWOSCALER_Pos 0U |
| |
| #define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
| |
| #define | TPI_FFCR_EnFmt_Pos 0U |
| |
| #define | TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) |
| |
| #define | TPI_PSCR_PSCount_Pos 0U |
| |
| #define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
| |
| #define | TPI_LSR_nTT_Pos 1U |
| |
| #define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
| |
| #define | TPI_LSR_SLK_Pos 1U |
| |
| #define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
| |
| #define | TPI_LSR_SLI_Pos 0U |
| |
| #define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | MPU_RBAR_ADDR_Pos 5U |
| |
| #define | MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
| |
| #define | MPU_RBAR_VALID_Pos 4U |
| |
| #define | MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
| |
| #define | MPU_RBAR_REGION_Pos 0U |
| |
| #define | MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
| |
| #define | MPU_RASR_ATTRS_Pos 16U |
| |
| #define | MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
| |
| #define | MPU_RASR_XN_Pos 28U |
| |
| #define | MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
| |
| #define | MPU_RASR_AP_Pos 24U |
| |
| #define | MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
| |
| #define | MPU_RASR_TEX_Pos 19U |
| |
| #define | MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
| |
| #define | MPU_RASR_S_Pos 18U |
| |
| #define | MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
| |
| #define | MPU_RASR_C_Pos 17U |
| |
| #define | MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
| |
| #define | MPU_RASR_B_Pos 16U |
| |
| #define | MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
| |
| #define | MPU_RASR_SRD_Pos 8U |
| |
| #define | MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
| |
| #define | MPU_RASR_SIZE_Pos 1U |
| |
| #define | MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
| |
| #define | MPU_RASR_ENABLE_Pos 0U |
| |
| #define | MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
| |
| #define | MPU_RBAR_ADDR_Pos 5U |
| |
| #define | MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
| |
| #define | MPU_RBAR_VALID_Pos 4U |
| |
| #define | MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
| |
| #define | MPU_RBAR_REGION_Pos 0U |
| |
| #define | MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
| |
| #define | MPU_RASR_ATTRS_Pos 16U |
| |
| #define | MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
| |
| #define | MPU_RASR_XN_Pos 28U |
| |
| #define | MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
| |
| #define | MPU_RASR_AP_Pos 24U |
| |
| #define | MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
| |
| #define | MPU_RASR_TEX_Pos 19U |
| |
| #define | MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
| |
| #define | MPU_RASR_S_Pos 18U |
| |
| #define | MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
| |
| #define | MPU_RASR_C_Pos 17U |
| |
| #define | MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
| |
| #define | MPU_RASR_B_Pos 16U |
| |
| #define | MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
| |
| #define | MPU_RASR_SRD_Pos 8U |
| |
| #define | MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
| |
| #define | MPU_RASR_SIZE_Pos 1U |
| |
| #define | MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
| |
| #define | MPU_RASR_ENABLE_Pos 0U |
| |
| #define | MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
| |
| #define | MPU_RBAR_ADDR_Pos 5U |
| |
| #define | MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
| |
| #define | MPU_RBAR_VALID_Pos 4U |
| |
| #define | MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
| |
| #define | MPU_RBAR_REGION_Pos 0U |
| |
| #define | MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
| |
| #define | MPU_RASR_ATTRS_Pos 16U |
| |
| #define | MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
| |
| #define | MPU_RASR_XN_Pos 28U |
| |
| #define | MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
| |
| #define | MPU_RASR_AP_Pos 24U |
| |
| #define | MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
| |
| #define | MPU_RASR_TEX_Pos 19U |
| |
| #define | MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
| |
| #define | MPU_RASR_S_Pos 18U |
| |
| #define | MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
| |
| #define | MPU_RASR_C_Pos 17U |
| |
| #define | MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
| |
| #define | MPU_RASR_B_Pos 16U |
| |
| #define | MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
| |
| #define | MPU_RASR_SRD_Pos 8U |
| |
| #define | MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
| |
| #define | MPU_RASR_SIZE_Pos 1U |
| |
| #define | MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
| |
| #define | MPU_RASR_ENABLE_Pos 0U |
| |
| #define | MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
| |
| #define | MPU_RLAR_PXN_Pos 4U |
| |
| #define | MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) |
| |
| #define | MPU_RBAR_ADDR_Pos 5U |
| |
| #define | MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) |
| |
| #define | MPU_RBAR_VALID_Pos 4U |
| |
| #define | MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
| |
| #define | MPU_RBAR_REGION_Pos 0U |
| |
| #define | MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
| |
| #define | MPU_RASR_ATTRS_Pos 16U |
| |
| #define | MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
| |
| #define | MPU_RASR_XN_Pos 28U |
| |
| #define | MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
| |
| #define | MPU_RASR_AP_Pos 24U |
| |
| #define | MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
| |
| #define | MPU_RASR_TEX_Pos 19U |
| |
| #define | MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
| |
| #define | MPU_RASR_S_Pos 18U |
| |
| #define | MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
| |
| #define | MPU_RASR_C_Pos 17U |
| |
| #define | MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
| |
| #define | MPU_RASR_B_Pos 16U |
| |
| #define | MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
| |
| #define | MPU_RASR_SRD_Pos 8U |
| |
| #define | MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
| |
| #define | MPU_RASR_SIZE_Pos 1U |
| |
| #define | MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
| |
| #define | MPU_RASR_ENABLE_Pos 0U |
| |
| #define | MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
| |
| #define | FPU_FPDSCR_FZ16_Pos 19U |
| |
| #define | FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) |
| |
| #define | FPU_FPDSCR_LTPSIZE_Pos 16U |
| |
| #define | FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) |
| |
| #define | FPU_MVFR0_FPRound_Pos 28U |
| |
| #define | FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) |
| |
| #define | FPU_MVFR0_FPSqrt_Pos 20U |
| |
| #define | FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) |
| |
| #define | FPU_MVFR0_FPDivide_Pos 16U |
| |
| #define | FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) |
| |
| #define | FPU_MVFR0_FPDP_Pos 8U |
| |
| #define | FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) |
| |
| #define | FPU_MVFR0_FPSP_Pos 4U |
| |
| #define | FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) |
| |
| #define | FPU_MVFR0_SIMDReg_Pos 0U |
| |
| #define | FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) |
| |
| #define | FPU_MVFR1_FMAC_Pos 28U |
| |
| #define | FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) |
| |
| #define | FPU_MVFR1_FPHP_Pos 24U |
| |
| #define | FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) |
| |
| #define | FPU_MVFR1_FP16_Pos 20U |
| |
| #define | FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) |
| |
| #define | FPU_MVFR1_MVE_Pos 8U |
| |
| #define | FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) |
| |
| #define | FPU_MVFR1_FPDNaN_Pos 4U |
| |
| #define | FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) |
| |
| #define | FPU_MVFR1_FPFtZ_Pos 0U |
| |
| #define | FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DHCSR_S_FPD_Pos 23U |
| |
| #define | CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| |
| #define | CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| |
| #define | CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| |
| #define | CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| |
| #define | CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| |
| #define | CoreDebug_DHCSR_S_SDE_Pos 20U |
| |
| #define | CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| |
| #define | CoreDebug_DHCSR_C_PMOV_Pos 6U |
| |
| #define | CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | DCB_DHCSR_S_FPD_Pos 23U |
| |
| #define | DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) |
| |
| #define | DCB_DHCSR_S_SUIDE_Pos 22U |
| |
| #define | DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) |
| |
| #define | DCB_DHCSR_S_NSUIDE_Pos 21U |
| |
| #define | DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) |
| |
| #define | DCB_DHCSR_C_PMOV_Pos 6U |
| |
| #define | DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) |
| |
| #define | DCB_DSCEMCR_CLR_MON_REQ_Pos 19U |
| |
| #define | DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) |
| |
| #define | DCB_DSCEMCR_CLR_MON_PEND_Pos 17U |
| |
| #define | DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) |
| |
| #define | DCB_DSCEMCR_SET_MON_REQ_Pos 3U |
| |
| #define | DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) |
| |
| #define | DCB_DSCEMCR_SET_MON_PEND_Pos 1U |
| |
| #define | DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) |
| |
| #define | DCB_DAUTHCTRL_UIDEN_Pos 10U |
| |
| #define | DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) |
| |
| #define | DCB_DAUTHCTRL_UIDAPEN_Pos 9U |
| |
| #define | DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) |
| |
| #define | DCB_DAUTHCTRL_FSDMA_Pos 8U |
| |
| #define | DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) |
| |
| #define | DIB_DAUTHSTATUS_SUNID_Pos 22U |
| |
| #define | DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_SUID_Pos 20U |
| |
| #define | DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_NSUNID_Pos 18U |
| |
| #define | DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_NSUID_Pos 16U |
| |
| #define | DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) |
| |
| #define | MEMSYSCTL_BASE (0xE001E000UL) |
| |
| #define | ERRBNK_BASE (0xE001E100UL) |
| |
| #define | PWRMODCTL_BASE (0xE001E300UL) |
| |
| #define | EWIC_BASE (0xE001E400UL) |
| |
| #define | PRCCFGINF_BASE (0xE001E700UL) |
| |
| #define | ICB ((ICB_Type *) SCS_BASE ) |
| |
| #define | MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) |
| |
| #define | ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) |
| |
| #define | PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) |
| |
| #define | EWIC ((EWIC_Type *) EWIC_BASE ) |
| |
| #define | PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
| #define | ICB_ACTLR_DISCRITAXIRUW_Pos 27U |
| |
| #define | ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) |
| |
| #define | ICB_ACTLR_DISCRITAXIRUR_Pos 15U |
| |
| #define | ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) |
| |
| #define | ICB_ACTLR_EVENTBUSEN_Pos 14U |
| |
| #define | ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) |
| |
| #define | ICB_ACTLR_EVENTBUSEN_S_Pos 13U |
| |
| #define | ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) |
| |
| #define | ICB_ACTLR_DISITMATBFLUSH_Pos 12U |
| |
| #define | ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) |
| |
| #define | ICB_ACTLR_DISNWAMODE_Pos 11U |
| |
| #define | ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) |
| |
| #define | ICB_ACTLR_FPEXCODIS_Pos 10U |
| |
| #define | ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) |
| |
| #define | ICB_ICTR_INTLINESNUM_Pos 0U |
| |
| #define | ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) |
| |
| #define | MEMSYSCTL_MSCR_CPWRDN_Pos 17U |
| |
| #define | MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) |
| |
| #define | MEMSYSCTL_MSCR_DCCLEAN_Pos 16U |
| |
| #define | MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) |
| |
| #define | MEMSYSCTL_MSCR_ICACTIVE_Pos 13U |
| |
| #define | MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) |
| |
| #define | MEMSYSCTL_MSCR_DCACTIVE_Pos 12U |
| |
| #define | MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) |
| |
| #define | MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U |
| |
| #define | MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) |
| |
| #define | MEMSYSCTL_MSCR_FORCEWT_Pos 2U |
| |
| #define | MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) |
| |
| #define | MEMSYSCTL_MSCR_ECCEN_Pos 1U |
| |
| #define | MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) |
| |
| #define | MEMSYSCTL_PFCR_DIS_NLP_Pos 7U |
| |
| #define | MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) |
| |
| #define | MEMSYSCTL_PFCR_ENABLE_Pos 0U |
| |
| #define | MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) |
| |
| #define | MEMSYSCTL_ITCMCR_SZ_Pos 3U |
| |
| #define | MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) |
| |
| #define | MEMSYSCTL_ITCMCR_EN_Pos 0U |
| |
| #define | MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) |
| |
| #define | MEMSYSCTL_DTCMCR_SZ_Pos 3U |
| |
| #define | MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) |
| |
| #define | MEMSYSCTL_DTCMCR_EN_Pos 0U |
| |
| #define | MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) |
| |
| #define | MEMSYSCTL_PAHBCR_SZ_Pos 1U |
| |
| #define | MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) |
| |
| #define | MEMSYSCTL_PAHBCR_EN_Pos 0U |
| |
| #define | MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) |
| |
| #define | MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U |
| |
| #define | MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) |
| |
| #define | MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U |
| |
| #define | MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) |
| |
| #define | MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U |
| |
| #define | MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) |
| |
| #define | MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U |
| |
| #define | MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) |
| |
| #define | MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U |
| |
| #define | MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) |
| |
| #define | MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U |
| |
| #define | MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) |
| |
| #define | PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U |
| |
| #define | PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) |
| |
| #define | PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U |
| |
| #define | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) |
| |
| #define | PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U |
| |
| #define | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) |
| |
| #define | PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U |
| |
| #define | PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) |
| |
| #define | EWIC_EVENTSPR_EDBGREQ_Pos 2U |
| |
| #define | EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) |
| |
| #define | EWIC_EVENTSPR_NMI_Pos 1U |
| |
| #define | EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) |
| |
| #define | EWIC_EVENTSPR_EVENT_Pos 0U |
| |
| #define | EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) |
| |
| #define | EWIC_EVENTMASKA_EDBGREQ_Pos 2U |
| |
| #define | EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) |
| |
| #define | EWIC_EVENTMASKA_NMI_Pos 1U |
| |
| #define | EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) |
| |
| #define | EWIC_EVENTMASKA_EVENT_Pos 0U |
| |
| #define | EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) |
| |
| #define | EWIC_EVENTMASK_IRQ_Pos 0U |
| |
| #define | EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) |
| |
| #define | ERRBNK_IEBR0_SWDEF_Pos 30U |
| |
| #define | ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
| |
| #define | ERRBNK_IEBR0_BANK_Pos 16U |
| |
| #define | ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
| |
| #define | ERRBNK_IEBR0_LOCATION_Pos 2U |
| |
| #define | ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
| |
| #define | ERRBNK_IEBR0_LOCKED_Pos 1U |
| |
| #define | ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
| |
| #define | ERRBNK_IEBR0_VALID_Pos 0U |
| |
| #define | ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
| |
| #define | ERRBNK_IEBR1_SWDEF_Pos 30U |
| |
| #define | ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
| |
| #define | ERRBNK_IEBR1_BANK_Pos 16U |
| |
| #define | ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
| |
| #define | ERRBNK_IEBR1_LOCATION_Pos 2U |
| |
| #define | ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
| |
| #define | ERRBNK_IEBR1_LOCKED_Pos 1U |
| |
| #define | ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
| |
| #define | ERRBNK_IEBR1_VALID_Pos 0U |
| |
| #define | ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
| |
| #define | ERRBNK_DEBR0_SWDEF_Pos 30U |
| |
| #define | ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
| |
| #define | ERRBNK_DEBR0_TYPE_Pos 17U |
| |
| #define | ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
| |
| #define | ERRBNK_DEBR0_BANK_Pos 16U |
| |
| #define | ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
| |
| #define | ERRBNK_DEBR0_LOCATION_Pos 2U |
| |
| #define | ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
| |
| #define | ERRBNK_DEBR0_LOCKED_Pos 1U |
| |
| #define | ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
| |
| #define | ERRBNK_DEBR0_VALID_Pos 0U |
| |
| #define | ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
| |
| #define | ERRBNK_DEBR1_SWDEF_Pos 30U |
| |
| #define | ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
| |
| #define | ERRBNK_DEBR1_TYPE_Pos 17U |
| |
| #define | ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
| |
| #define | ERRBNK_DEBR1_BANK_Pos 16U |
| |
| #define | ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
| |
| #define | ERRBNK_DEBR1_LOCATION_Pos 2U |
| |
| #define | ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
| |
| #define | ERRBNK_DEBR1_LOCKED_Pos 1U |
| |
| #define | ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
| |
| #define | ERRBNK_DEBR1_VALID_Pos 0U |
| |
| #define | ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
| |
| #define | ERRBNK_TEBR0_SWDEF_Pos 30U |
| |
| #define | ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
| |
| #define | ERRBNK_TEBR0_POISON_Pos 28U |
| |
| #define | ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
| |
| #define | ERRBNK_TEBR0_TYPE_Pos 27U |
| |
| #define | ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
| |
| #define | ERRBNK_TEBR0_BANK_Pos 24U |
| |
| #define | ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
| |
| #define | ERRBNK_TEBR0_LOCATION_Pos 2U |
| |
| #define | ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
| |
| #define | ERRBNK_TEBR0_LOCKED_Pos 1U |
| |
| #define | ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
| |
| #define | ERRBNK_TEBR0_VALID_Pos 0U |
| |
| #define | ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
| |
| #define | ERRBNK_TEBR1_SWDEF_Pos 30U |
| |
| #define | ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
| |
| #define | ERRBNK_TEBR1_POISON_Pos 28U |
| |
| #define | ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
| |
| #define | ERRBNK_TEBR1_TYPE_Pos 27U |
| |
| #define | ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
| |
| #define | ERRBNK_TEBR1_BANK_Pos 24U |
| |
| #define | ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
| |
| #define | ERRBNK_TEBR1_LOCATION_Pos 2U |
| |
| #define | ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
| |
| #define | ERRBNK_TEBR1_LOCKED_Pos 1U |
| |
| #define | ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
| |
| #define | ERRBNK_TEBR1_VALID_Pos 0U |
| |
| #define | ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_NSACR_CPn_Pos 0U |
| |
| #define | SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_NSACR_CPn_Pos 0U |
| |
| #define | SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_NSACR_CPn_Pos 0U |
| |
| #define | SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_ITCMCR_SZ_Pos 3U |
| |
| #define | SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
| |
| #define | SCB_ITCMCR_EN_Pos 0U |
| |
| #define | SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
| |
| #define | SCB_DTCMCR_SZ_Pos 3U |
| |
| #define | SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
| |
| #define | SCB_DTCMCR_EN_Pos 0U |
| |
| #define | SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
| |
| #define | SCB_CACR_FORCEWT_Pos 2U |
| |
| #define | SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| |
| #define | SCB_CPUID_REVISION_Pos 0U |
| |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| |
| #define | SCB_ICSR_PENDNMISET_Pos 31U |
| |
| #define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
| |
| #define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
| |
| #define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
| |
| #define | SCB_ICSR_PENDNMICLR_Pos 30U |
| |
| #define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
| |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| |
| #define | SCB_ICSR_STTNS_Pos 24U |
| |
| #define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
| |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| |
| #define | SCB_ICSR_RETTOBASE_Pos 11U |
| |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| |
| #define | SCB_VTOR_TBLOFF_Pos 7U |
| |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| |
| #define | SCB_AIRCR_PRIS_Pos 14U |
| |
| #define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
| |
| #define | SCB_AIRCR_BFHFNMINS_Pos 13U |
| |
| #define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
| |
| #define | SCB_AIRCR_PRIGROUP_Pos 8U |
| |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Pos 3U |
| |
| #define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEPS_Pos 3U |
| |
| #define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
| |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| |
| #define | SCB_CCR_BP_Pos 18U |
| |
| #define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
| |
| #define | SCB_CCR_IC_Pos 17U |
| |
| #define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
| |
| #define | SCB_CCR_DC_Pos 16U |
| |
| #define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Pos 10U |
| |
| #define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_BFHFNMIGN_Pos 8U |
| |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| |
| #define | SCB_CCR_DIV_0_TRP_Pos 4U |
| |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| |
| #define | SCB_CCR_USERSETMPEND_Pos 1U |
| |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
| |
| #define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
| |
| #define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Pos 19U |
| |
| #define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18U |
| |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17U |
| |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16U |
| |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
| |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
| |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12U |
| |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11U |
| |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| |
| #define | SCB_SHCSR_PENDSVACT_Pos 10U |
| |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| |
| #define | SCB_SHCSR_MONITORACT_Pos 8U |
| |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| |
| #define | SCB_SHCSR_SVCALLACT_Pos 7U |
| |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| |
| #define | SCB_SHCSR_NMIACT_Pos 5U |
| |
| #define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Pos 4U |
| |
| #define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3U |
| |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Pos 2U |
| |
| #define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1U |
| |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0U |
| |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
| |
| #define | SCB_CFSR_USGFAULTSR_Pos 16U |
| |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8U |
| |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0U |
| |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
| |
| #define | SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
| |
| #define | SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
| |
| #define | SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
| |
| #define | SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
| |
| #define | SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
| |
| #define | SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
| |
| #define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
| |
| #define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
| |
| #define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
| |
| #define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
| |
| #define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
| |
| #define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
| |
| #define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
| |
| #define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
| |
| #define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
| |
| #define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
| |
| #define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
| |
| #define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
| |
| #define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
| |
| #define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
| |
| #define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
| |
| #define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
| |
| #define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
| |
| #define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
| |
| #define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
| |
| #define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
| |
| #define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
| |
| #define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
| |
| #define | SCB_HFSR_DEBUGEVT_Pos 31U |
| |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| |
| #define | SCB_HFSR_FORCED_Pos 30U |
| |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| |
| #define | SCB_HFSR_VECTTBL_Pos 1U |
| |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| |
| #define | SCB_DFSR_EXTERNAL_Pos 4U |
| |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| |
| #define | SCB_DFSR_VCATCH_Pos 3U |
| |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| |
| #define | SCB_DFSR_DWTTRAP_Pos 2U |
| |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| |
| #define | SCB_DFSR_BKPT_Pos 1U |
| |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| |
| #define | SCB_DFSR_HALTED_Pos 0U |
| |
| #define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
| |
| #define | SCB_NSACR_CP11_Pos 11U |
| |
| #define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
| |
| #define | SCB_NSACR_CP10_Pos 10U |
| |
| #define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
| |
| #define | SCB_NSACR_CPn_Pos 0U |
| |
| #define | SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
| |
| #define | SCB_CLIDR_LOUU_Pos 27U |
| |
| #define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
| |
| #define | SCB_CLIDR_LOC_Pos 24U |
| |
| #define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
| |
| #define | SCB_CLIDR_IC_Pos 0U |
| |
| #define | SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) |
| |
| #define | SCB_CLIDR_DC_Pos 1U |
| |
| #define | SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) |
| |
| #define | SCB_CTR_FORMAT_Pos 29U |
| |
| #define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
| |
| #define | SCB_CTR_CWG_Pos 24U |
| |
| #define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
| |
| #define | SCB_CTR_ERG_Pos 20U |
| |
| #define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
| |
| #define | SCB_CTR_DMINLINE_Pos 16U |
| |
| #define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
| |
| #define | SCB_CTR_IMINLINE_Pos 0U |
| |
| #define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
| |
| #define | SCB_CCSIDR_WT_Pos 31U |
| |
| #define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
| |
| #define | SCB_CCSIDR_WB_Pos 30U |
| |
| #define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
| |
| #define | SCB_CCSIDR_RA_Pos 29U |
| |
| #define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
| |
| #define | SCB_CCSIDR_WA_Pos 28U |
| |
| #define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
| |
| #define | SCB_CCSIDR_NUMSETS_Pos 13U |
| |
| #define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
| |
| #define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| |
| #define | SCB_CCSIDR_LINESIZE_Pos 0U |
| |
| #define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
| |
| #define | SCB_CSSELR_LEVEL_Pos 1U |
| |
| #define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
| |
| #define | SCB_CSSELR_IND_Pos 0U |
| |
| #define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
| |
| #define | SCB_STIR_INTID_Pos 0U |
| |
| #define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
| |
| #define | SCB_DCISW_LEVEL_Pos 1U |
| |
| #define | SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) |
| |
| #define | SCB_DCISW_WAY_Pos 30U |
| |
| #define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
| |
| #define | SCB_DCISW_SET_Pos 5U |
| |
| #define | SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) |
| |
| #define | SCB_DCCSW_LEVEL_Pos 1U |
| |
| #define | SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) |
| |
| #define | SCB_DCCSW_WAY_Pos 30U |
| |
| #define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
| |
| #define | SCB_DCCSW_SET_Pos 5U |
| |
| #define | SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) |
| |
| #define | SCB_DCCISW_LEVEL_Pos 1U |
| |
| #define | SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) |
| |
| #define | SCB_DCCISW_WAY_Pos 30U |
| |
| #define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
| |
| #define | SCB_DCCISW_SET_Pos 5U |
| |
| #define | SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) |
| |
| #define | SCB_ITCMCR_SZ_Pos 3U |
| |
| #define | SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
| |
| #define | SCB_ITCMCR_EN_Pos 0U |
| |
| #define | SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
| |
| #define | SCB_DTCMCR_SZ_Pos 3U |
| |
| #define | SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
| |
| #define | SCB_DTCMCR_EN_Pos 0U |
| |
| #define | SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
| |
| #define | SCB_CACR_DCCLEAN_Pos 16U |
| |
| #define | SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
| |
| #define | SCB_CACR_ICACTIVE_Pos 13U |
| |
| #define | SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
| |
| #define | SCB_CACR_DCACTIVE_Pos 12U |
| |
| #define | SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
| |
| #define | SCB_CACR_FORCEWT_Pos 2U |
| |
| #define | SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
| |
| #define | SCB_AIRCR_IESB_Pos 5U |
| |
| #define | SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) |
| |
| #define | SCB_AIRCR_DIT_Pos 4U |
| |
| #define | SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) |
| |
| #define | SCB_CCR_TRD_Pos 20U |
| |
| #define | SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) |
| |
| #define | SCB_CCR_LOB_Pos 19U |
| |
| #define | SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) |
| |
| #define | SCB_DFSR_PMU_Pos 5U |
| |
| #define | SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) |
| |
| #define | SCB_NSACR_CP7_Pos 7U |
| |
| #define | SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) |
| |
| #define | SCB_NSACR_CP6_Pos 6U |
| |
| #define | SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) |
| |
| #define | SCB_NSACR_CP5_Pos 5U |
| |
| #define | SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) |
| |
| #define | SCB_NSACR_CP4_Pos 4U |
| |
| #define | SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) |
| |
| #define | SCB_NSACR_CP3_Pos 3U |
| |
| #define | SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) |
| |
| #define | SCB_NSACR_CP2_Pos 2U |
| |
| #define | SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) |
| |
| #define | SCB_NSACR_CP1_Pos 1U |
| |
| #define | SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) |
| |
| #define | SCB_NSACR_CP0_Pos 0U |
| |
| #define | SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) |
| |
| #define | SCB_ID_DFR_UDE_Pos 28U |
| |
| #define | SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) |
| |
| #define | SCB_ID_DFR_MProfDbg_Pos 20U |
| |
| #define | SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) |
| |
| #define | SCB_RFSR_V_Pos 31U |
| |
| #define | SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) |
| |
| #define | SCB_RFSR_IS_Pos 16U |
| |
| #define | SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) |
| |
| #define | SCB_RFSR_UET_Pos 0U |
| |
| #define | SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) |
| |
| #define | SCB_AIRCR_IESB_Pos 5U |
| |
| #define | SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) |
| |
| #define | SCB_AIRCR_DIT_Pos 4U |
| |
| #define | SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) |
| |
| #define | SCB_CCR_TRD_Pos 20U |
| |
| #define | SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) |
| |
| #define | SCB_CCR_LOB_Pos 19U |
| |
| #define | SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) |
| |
| #define | SCB_DFSR_PMU_Pos 5U |
| |
| #define | SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) |
| |
| #define | SCB_NSACR_CP7_Pos 7U |
| |
| #define | SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) |
| |
| #define | SCB_NSACR_CP6_Pos 6U |
| |
| #define | SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) |
| |
| #define | SCB_NSACR_CP5_Pos 5U |
| |
| #define | SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) |
| |
| #define | SCB_NSACR_CP4_Pos 4U |
| |
| #define | SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) |
| |
| #define | SCB_NSACR_CP3_Pos 3U |
| |
| #define | SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) |
| |
| #define | SCB_NSACR_CP2_Pos 2U |
| |
| #define | SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) |
| |
| #define | SCB_NSACR_CP1_Pos 1U |
| |
| #define | SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) |
| |
| #define | SCB_NSACR_CP0_Pos 0U |
| |
| #define | SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) |
| |
| #define | SCB_ID_DFR_UDE_Pos 28U |
| |
| #define | SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) |
| |
| #define | SCB_ID_DFR_MProfDbg_Pos 20U |
| |
| #define | SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) |
| |
| #define | SCB_RFSR_V_Pos 31U |
| |
| #define | SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) |
| |
| #define | SCB_RFSR_IS_Pos 16U |
| |
| #define | SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) |
| |
| #define | SCB_RFSR_UET_Pos 0U |
| |
| #define | SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) |
| |
| #define | SCB_AIRCR_IESB_Pos 5U |
| |
| #define | SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) |
| |
| #define | SCB_AIRCR_DIT_Pos 4U |
| |
| #define | SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) |
| |
| #define | SCB_CCR_TRD_Pos 20U |
| |
| #define | SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) |
| |
| #define | SCB_CCR_LOB_Pos 19U |
| |
| #define | SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) |
| |
| #define | SCB_DFSR_PMU_Pos 5U |
| |
| #define | SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) |
| |
| #define | SCB_NSACR_CP7_Pos 7U |
| |
| #define | SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) |
| |
| #define | SCB_NSACR_CP6_Pos 6U |
| |
| #define | SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) |
| |
| #define | SCB_NSACR_CP5_Pos 5U |
| |
| #define | SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) |
| |
| #define | SCB_NSACR_CP4_Pos 4U |
| |
| #define | SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) |
| |
| #define | SCB_NSACR_CP3_Pos 3U |
| |
| #define | SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) |
| |
| #define | SCB_NSACR_CP2_Pos 2U |
| |
| #define | SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) |
| |
| #define | SCB_NSACR_CP1_Pos 1U |
| |
| #define | SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) |
| |
| #define | SCB_NSACR_CP0_Pos 0U |
| |
| #define | SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) |
| |
| #define | SCB_ID_DFR_UDE_Pos 28U |
| |
| #define | SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) |
| |
| #define | SCB_ID_DFR_MProfDbg_Pos 20U |
| |
| #define | SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) |
| |
| #define | SCB_RFSR_V_Pos 31U |
| |
| #define | SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) |
| |
| #define | SCB_RFSR_IS_Pos 16U |
| |
| #define | SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) |
| |
| #define | SCB_RFSR_UET_Pos 0U |
| |
| #define | SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) |
| |
| #define | TPI_ACPR_SWOSCALER_Pos 0U |
| |
| #define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
| |
| #define | TPI_FFCR_EnFmt_Pos 0U |
| |
| #define | TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) |
| |
| #define | TPI_PSCR_PSCount_Pos 0U |
| |
| #define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
| |
| #define | TPI_LSR_nTT_Pos 1U |
| |
| #define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
| |
| #define | TPI_LSR_SLK_Pos 1U |
| |
| #define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
| |
| #define | TPI_LSR_SLI_Pos 0U |
| |
| #define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
| |
| #define | MPU_RLAR_PXN_Pos 4U |
| |
| #define | MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) |
| |
| #define | FPU_FPDSCR_FZ16_Pos 19U |
| |
| #define | FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) |
| |
| #define | FPU_FPDSCR_LTPSIZE_Pos 16U |
| |
| #define | FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) |
| |
| #define | FPU_MVFR0_FPRound_Pos 28U |
| |
| #define | FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) |
| |
| #define | FPU_MVFR0_FPSqrt_Pos 20U |
| |
| #define | FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) |
| |
| #define | FPU_MVFR0_FPDivide_Pos 16U |
| |
| #define | FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) |
| |
| #define | FPU_MVFR0_FPDP_Pos 8U |
| |
| #define | FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) |
| |
| #define | FPU_MVFR0_FPSP_Pos 4U |
| |
| #define | FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) |
| |
| #define | FPU_MVFR0_SIMDReg_Pos 0U |
| |
| #define | FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) |
| |
| #define | FPU_MVFR1_FMAC_Pos 28U |
| |
| #define | FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) |
| |
| #define | FPU_MVFR1_FPHP_Pos 24U |
| |
| #define | FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) |
| |
| #define | FPU_MVFR1_FP16_Pos 20U |
| |
| #define | FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) |
| |
| #define | FPU_MVFR1_MVE_Pos 8U |
| |
| #define | FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) |
| |
| #define | FPU_MVFR1_FPDNaN_Pos 4U |
| |
| #define | FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) |
| |
| #define | FPU_MVFR1_FPFtZ_Pos 0U |
| |
| #define | FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DHCSR_S_FPD_Pos 23U |
| |
| #define | CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| |
| #define | CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| |
| #define | CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| |
| #define | CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| |
| #define | CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| |
| #define | CoreDebug_DHCSR_S_SDE_Pos 20U |
| |
| #define | CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| |
| #define | CoreDebug_DHCSR_C_PMOV_Pos 6U |
| |
| #define | CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | DCB_DHCSR_S_FPD_Pos 23U |
| |
| #define | DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) |
| |
| #define | DCB_DHCSR_S_SUIDE_Pos 22U |
| |
| #define | DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) |
| |
| #define | DCB_DHCSR_S_NSUIDE_Pos 21U |
| |
| #define | DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) |
| |
| #define | DCB_DHCSR_C_PMOV_Pos 6U |
| |
| #define | DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) |
| |
| #define | DCB_DSCEMCR_CLR_MON_REQ_Pos 19U |
| |
| #define | DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) |
| |
| #define | DCB_DSCEMCR_CLR_MON_PEND_Pos 17U |
| |
| #define | DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) |
| |
| #define | DCB_DSCEMCR_SET_MON_REQ_Pos 3U |
| |
| #define | DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) |
| |
| #define | DCB_DSCEMCR_SET_MON_PEND_Pos 1U |
| |
| #define | DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) |
| |
| #define | DCB_DAUTHCTRL_UIDEN_Pos 10U |
| |
| #define | DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) |
| |
| #define | DCB_DAUTHCTRL_UIDAPEN_Pos 9U |
| |
| #define | DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) |
| |
| #define | DCB_DAUTHCTRL_FSDMA_Pos 8U |
| |
| #define | DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) |
| |
| #define | DIB_DAUTHSTATUS_SUNID_Pos 22U |
| |
| #define | DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_SUID_Pos 20U |
| |
| #define | DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_NSUNID_Pos 18U |
| |
| #define | DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_NSUID_Pos 16U |
| |
| #define | DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) |
| |
| #define | ICB_ACTLR_DISCRITAXIRUW_Pos 27U |
| |
| #define | ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) |
| |
| #define | ICB_ACTLR_DISCRITAXIRUR_Pos 15U |
| |
| #define | ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) |
| |
| #define | ICB_ACTLR_EVENTBUSEN_Pos 14U |
| |
| #define | ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) |
| |
| #define | ICB_ACTLR_EVENTBUSEN_S_Pos 13U |
| |
| #define | ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) |
| |
| #define | ICB_ACTLR_DISITMATBFLUSH_Pos 12U |
| |
| #define | ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) |
| |
| #define | ICB_ACTLR_DISNWAMODE_Pos 11U |
| |
| #define | ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) |
| |
| #define | ICB_ACTLR_FPEXCODIS_Pos 10U |
| |
| #define | ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) |
| |
| #define | ICB_ICTR_INTLINESNUM_Pos 0U |
| |
| #define | ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) |
| |
| #define | MEMSYSCTL_MSCR_CPWRDN_Pos 17U |
| |
| #define | MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) |
| |
| #define | MEMSYSCTL_MSCR_DCCLEAN_Pos 16U |
| |
| #define | MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) |
| |
| #define | MEMSYSCTL_MSCR_ICACTIVE_Pos 13U |
| |
| #define | MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) |
| |
| #define | MEMSYSCTL_MSCR_DCACTIVE_Pos 12U |
| |
| #define | MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) |
| |
| #define | MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U |
| |
| #define | MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) |
| |
| #define | MEMSYSCTL_MSCR_FORCEWT_Pos 2U |
| |
| #define | MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) |
| |
| #define | MEMSYSCTL_MSCR_ECCEN_Pos 1U |
| |
| #define | MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) |
| |
| #define | MEMSYSCTL_PFCR_ENABLE_Pos 0U |
| |
| #define | MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) |
| |
| #define | MEMSYSCTL_ITCMCR_SZ_Pos 3U |
| |
| #define | MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) |
| |
| #define | MEMSYSCTL_ITCMCR_EN_Pos 0U |
| |
| #define | MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) |
| |
| #define | MEMSYSCTL_DTCMCR_SZ_Pos 3U |
| |
| #define | MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) |
| |
| #define | MEMSYSCTL_DTCMCR_EN_Pos 0U |
| |
| #define | MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) |
| |
| #define | MEMSYSCTL_PAHBCR_SZ_Pos 1U |
| |
| #define | MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) |
| |
| #define | MEMSYSCTL_PAHBCR_EN_Pos 0U |
| |
| #define | MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U |
| |
| #define | MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) |
| |
| #define | MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U |
| |
| #define | MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) |
| |
| #define | MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U |
| |
| #define | MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) |
| |
| #define | MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U |
| |
| #define | MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U |
| |
| #define | MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) |
| |
| #define | MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U |
| |
| #define | MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) |
| |
| #define | MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U |
| |
| #define | MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) |
| |
| #define | MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U |
| |
| #define | MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) |
| |
| #define | PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U |
| |
| #define | PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) |
| |
| #define | PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U |
| |
| #define | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) |
| |
| #define | PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U |
| |
| #define | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) |
| |
| #define | PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U |
| |
| #define | PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) |
| |
| #define | EWIC_EVENTSPR_EDBGREQ_Pos 2U |
| |
| #define | EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) |
| |
| #define | EWIC_EVENTSPR_NMI_Pos 1U |
| |
| #define | EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) |
| |
| #define | EWIC_EVENTSPR_EVENT_Pos 0U |
| |
| #define | EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) |
| |
| #define | EWIC_EVENTMASKA_EDBGREQ_Pos 2U |
| |
| #define | EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) |
| |
| #define | EWIC_EVENTMASKA_NMI_Pos 1U |
| |
| #define | EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) |
| |
| #define | EWIC_EVENTMASKA_EVENT_Pos 0U |
| |
| #define | EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) |
| |
| #define | EWIC_EVENTMASK_IRQ_Pos 0U |
| |
| #define | EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) |
| |
| #define | ERRBNK_IEBR0_SWDEF_Pos 30U |
| |
| #define | ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
| |
| #define | ERRBNK_IEBR0_BANK_Pos 16U |
| |
| #define | ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
| |
| #define | ERRBNK_IEBR0_LOCATION_Pos 2U |
| |
| #define | ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
| |
| #define | ERRBNK_IEBR0_LOCKED_Pos 1U |
| |
| #define | ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
| |
| #define | ERRBNK_IEBR0_VALID_Pos 0U |
| |
| #define | ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
| |
| #define | ERRBNK_IEBR1_SWDEF_Pos 30U |
| |
| #define | ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
| |
| #define | ERRBNK_IEBR1_BANK_Pos 16U |
| |
| #define | ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
| |
| #define | ERRBNK_IEBR1_LOCATION_Pos 2U |
| |
| #define | ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
| |
| #define | ERRBNK_IEBR1_LOCKED_Pos 1U |
| |
| #define | ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
| |
| #define | ERRBNK_IEBR1_VALID_Pos 0U |
| |
| #define | ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
| |
| #define | ERRBNK_DEBR0_SWDEF_Pos 30U |
| |
| #define | ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
| |
| #define | ERRBNK_DEBR0_TYPE_Pos 17U |
| |
| #define | ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
| |
| #define | ERRBNK_DEBR0_BANK_Pos 16U |
| |
| #define | ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
| |
| #define | ERRBNK_DEBR0_LOCATION_Pos 2U |
| |
| #define | ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
| |
| #define | ERRBNK_DEBR0_LOCKED_Pos 1U |
| |
| #define | ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
| |
| #define | ERRBNK_DEBR0_VALID_Pos 0U |
| |
| #define | ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
| |
| #define | ERRBNK_DEBR1_SWDEF_Pos 30U |
| |
| #define | ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
| |
| #define | ERRBNK_DEBR1_TYPE_Pos 17U |
| |
| #define | ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
| |
| #define | ERRBNK_DEBR1_BANK_Pos 16U |
| |
| #define | ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
| |
| #define | ERRBNK_DEBR1_LOCATION_Pos 2U |
| |
| #define | ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
| |
| #define | ERRBNK_DEBR1_LOCKED_Pos 1U |
| |
| #define | ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
| |
| #define | ERRBNK_DEBR1_VALID_Pos 0U |
| |
| #define | ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
| |
| #define | ERRBNK_TEBR0_SWDEF_Pos 30U |
| |
| #define | ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
| |
| #define | ERRBNK_TEBR0_POISON_Pos 28U |
| |
| #define | ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
| |
| #define | ERRBNK_TEBR0_TYPE_Pos 27U |
| |
| #define | ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
| |
| #define | ERRBNK_TEBR0_BANK_Pos 24U |
| |
| #define | ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
| |
| #define | ERRBNK_TEBR0_LOCATION_Pos 2U |
| |
| #define | ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
| |
| #define | ERRBNK_TEBR0_LOCKED_Pos 1U |
| |
| #define | ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
| |
| #define | ERRBNK_TEBR0_VALID_Pos 0U |
| |
| #define | ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
| |
| #define | ERRBNK_TEBR1_SWDEF_Pos 30U |
| |
| #define | ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
| |
| #define | ERRBNK_TEBR1_POISON_Pos 28U |
| |
| #define | ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
| |
| #define | ERRBNK_TEBR1_TYPE_Pos 27U |
| |
| #define | ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
| |
| #define | ERRBNK_TEBR1_BANK_Pos 24U |
| |
| #define | ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
| |
| #define | ERRBNK_TEBR1_LOCATION_Pos 2U |
| |
| #define | ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
| |
| #define | ERRBNK_TEBR1_LOCKED_Pos 1U |
| |
| #define | ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
| |
| #define | ERRBNK_TEBR1_VALID_Pos 0U |
| |
| #define | ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
| |
| #define | TPI_ACPR_SWOSCALER_Pos 0U |
| |
| #define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
| |
| #define | TPI_FFCR_EnFmt_Pos 0U |
| |
| #define | TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) |
| |
| #define | TPI_PSCR_PSCount_Pos 0U |
| |
| #define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
| |
| #define | TPI_LSR_nTT_Pos 1U |
| |
| #define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
| |
| #define | TPI_LSR_SLK_Pos 1U |
| |
| #define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
| |
| #define | TPI_LSR_SLI_Pos 0U |
| |
| #define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
| |
| #define | MPU_RLAR_PXN_Pos 4U |
| |
| #define | MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) |
| |
| #define | FPU_FPDSCR_FZ16_Pos 19U |
| |
| #define | FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) |
| |
| #define | FPU_FPDSCR_LTPSIZE_Pos 16U |
| |
| #define | FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) |
| |
| #define | FPU_MVFR0_FPRound_Pos 28U |
| |
| #define | FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) |
| |
| #define | FPU_MVFR0_FPSqrt_Pos 20U |
| |
| #define | FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) |
| |
| #define | FPU_MVFR0_FPDivide_Pos 16U |
| |
| #define | FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) |
| |
| #define | FPU_MVFR0_FPDP_Pos 8U |
| |
| #define | FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) |
| |
| #define | FPU_MVFR0_FPSP_Pos 4U |
| |
| #define | FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) |
| |
| #define | FPU_MVFR0_SIMDReg_Pos 0U |
| |
| #define | FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) |
| |
| #define | FPU_MVFR1_FMAC_Pos 28U |
| |
| #define | FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) |
| |
| #define | FPU_MVFR1_FPHP_Pos 24U |
| |
| #define | FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) |
| |
| #define | FPU_MVFR1_FP16_Pos 20U |
| |
| #define | FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) |
| |
| #define | FPU_MVFR1_MVE_Pos 8U |
| |
| #define | FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) |
| |
| #define | FPU_MVFR1_FPDNaN_Pos 4U |
| |
| #define | FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) |
| |
| #define | FPU_MVFR1_FPFtZ_Pos 0U |
| |
| #define | FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| |
| #define | CoreDebug_DHCSR_S_FPD_Pos 23U |
| |
| #define | CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| |
| #define | CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| |
| #define | CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| |
| #define | CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| |
| #define | CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| |
| #define | CoreDebug_DHCSR_S_SDE_Pos 20U |
| |
| #define | CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| |
| #define | CoreDebug_DHCSR_C_PMOV_Pos 6U |
| |
| #define | CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| |
| #define | DCB_DHCSR_S_FPD_Pos 23U |
| |
| #define | DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) |
| |
| #define | DCB_DHCSR_S_SUIDE_Pos 22U |
| |
| #define | DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) |
| |
| #define | DCB_DHCSR_S_NSUIDE_Pos 21U |
| |
| #define | DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) |
| |
| #define | DCB_DHCSR_C_PMOV_Pos 6U |
| |
| #define | DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) |
| |
| #define | DCB_DSCEMCR_CLR_MON_REQ_Pos 19U |
| |
| #define | DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) |
| |
| #define | DCB_DSCEMCR_CLR_MON_PEND_Pos 17U |
| |
| #define | DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) |
| |
| #define | DCB_DSCEMCR_SET_MON_REQ_Pos 3U |
| |
| #define | DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) |
| |
| #define | DCB_DSCEMCR_SET_MON_PEND_Pos 1U |
| |
| #define | DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) |
| |
| #define | DCB_DAUTHCTRL_UIDEN_Pos 10U |
| |
| #define | DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) |
| |
| #define | DCB_DAUTHCTRL_UIDAPEN_Pos 9U |
| |
| #define | DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) |
| |
| #define | DCB_DAUTHCTRL_FSDMA_Pos 8U |
| |
| #define | DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) |
| |
| #define | DIB_DAUTHSTATUS_SUNID_Pos 22U |
| |
| #define | DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_SUID_Pos 20U |
| |
| #define | DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_NSUNID_Pos 18U |
| |
| #define | DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) |
| |
| #define | DIB_DAUTHSTATUS_NSUID_Pos 16U |
| |
| #define | DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) |
| |
| #define | MEMSYSCTL_BASE (0xE001E000UL) |
| |
| #define | ERRBNK_BASE (0xE001E100UL) |
| |
| #define | PWRMODCTL_BASE (0xE001E300UL) |
| |
| #define | EWIC_BASE (0xE001E400UL) |
| |
| #define | PRCCFGINF_BASE (0xE001E700UL) |
| |
| #define | ICB ((ICB_Type *) SCS_BASE ) |
| |
| #define | MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) |
| |
| #define | ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) |
| |
| #define | PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) |
| |
| #define | EWIC ((EWIC_Type *) EWIC_BASE ) |
| |
| #define | PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_AIRCR_VECTRESET_Pos 0U |
| |
| #define | SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_CCR_NONBASETHRDENA_Pos 0U |
| |
| #define | SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
| |
| #define | SCB_AIRCR_VECTRESET_Pos 0U |
| |
| #define | SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_CCR_NONBASETHRDENA_Pos 0U |
| |
| #define | SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
| |
| #define | SCB_AIRCR_VECTRESET_Pos 0U |
| |
| #define | SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_CCR_NONBASETHRDENA_Pos 0U |
| |
| #define | SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_VTOR_TBLBASE_Pos 29U |
| |
| #define | SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) |
| |
| #define | SCB_AIRCR_VECTRESET_Pos 0U |
| |
| #define | SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
| |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| |
| #define | SCB_CCR_NONBASETHRDENA_Pos 0U |
| |
| #define | SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
| #define | MPU_RBAR_ADDR_Pos 8U |
| |
| #define | MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) |
| |
| #define | MPU_RBAR_VALID_Pos 4U |
| |
| #define | MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
| |
| #define | MPU_RBAR_REGION_Pos 0U |
| |
| #define | MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
| |
| #define | MPU_RASR_ATTRS_Pos 16U |
| |
| #define | MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
| |
| #define | MPU_RASR_XN_Pos 28U |
| |
| #define | MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
| |
| #define | MPU_RASR_AP_Pos 24U |
| |
| #define | MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
| |
| #define | MPU_RASR_TEX_Pos 19U |
| |
| #define | MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
| |
| #define | MPU_RASR_S_Pos 18U |
| |
| #define | MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
| |
| #define | MPU_RASR_C_Pos 17U |
| |
| #define | MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
| |
| #define | MPU_RASR_B_Pos 16U |
| |
| #define | MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
| |
| #define | MPU_RASR_SRD_Pos 8U |
| |
| #define | MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
| |
| #define | MPU_RASR_SIZE_Pos 1U |
| |
| #define | MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
| |
| #define | MPU_RASR_ENABLE_Pos 0U |
| |
| #define | MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
| #define | SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
| |
| #define | SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
| |
| #define | MPU_RBAR_ADDR_Pos 8U |
| |
| #define | MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) |
| |
| #define | MPU_RBAR_VALID_Pos 4U |
| |
| #define | MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) |
| |
| #define | MPU_RBAR_REGION_Pos 0U |
| |
| #define | MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) |
| |
| #define | MPU_RASR_ATTRS_Pos 16U |
| |
| #define | MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) |
| |
| #define | MPU_RASR_XN_Pos 28U |
| |
| #define | MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) |
| |
| #define | MPU_RASR_AP_Pos 24U |
| |
| #define | MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) |
| |
| #define | MPU_RASR_TEX_Pos 19U |
| |
| #define | MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) |
| |
| #define | MPU_RASR_S_Pos 18U |
| |
| #define | MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) |
| |
| #define | MPU_RASR_C_Pos 17U |
| |
| #define | MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) |
| |
| #define | MPU_RASR_B_Pos 16U |
| |
| #define | MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) |
| |
| #define | MPU_RASR_SRD_Pos 8U |
| |
| #define | MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) |
| |
| #define | MPU_RASR_SIZE_Pos 1U |
| |
| #define | MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) |
| |
| #define | MPU_RASR_ENABLE_Pos 0U |
| |
| #define | MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) |
| |
|
#define | EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| |
|
#define | EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
| #define | SCB_ITCMCR_RETEN_Pos 2U |
| |
| #define | SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) |
| |
| #define | SCB_ITCMCR_RMW_Pos 1U |
| |
| #define | SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) |
| |
| #define | SCB_DTCMCR_RETEN_Pos 2U |
| |
| #define | SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) |
| |
| #define | SCB_DTCMCR_RMW_Pos 1U |
| |
| #define | SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) |
| |
| #define | SCB_AHBPCR_SZ_Pos 1U |
| |
| #define | SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) |
| |
| #define | SCB_AHBPCR_EN_Pos 0U |
| |
| #define | SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) |
| |
| #define | SCB_CACR_ECCEN_Pos 1U |
| |
| #define | SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) |
| |
| #define | SCB_CACR_ECCDIS_Pos 1U |
| |
| #define | SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) |
| |
| #define | SCB_CACR_SIWT_Pos 0U |
| |
| #define | SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) |
| |
| #define | SCB_AHBSCR_INITCOUNT_Pos 11U |
| |
| #define | SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) |
| |
| #define | SCB_AHBSCR_TPRI_Pos 2U |
| |
| #define | SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) |
| |
| #define | SCB_AHBSCR_CTL_Pos 0U |
| |
| #define | SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) |
| |
| #define | SCB_ABFSR_AXIMTYPE_Pos 8U |
| |
| #define | SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) |
| |
| #define | SCB_ABFSR_EPPB_Pos 4U |
| |
| #define | SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) |
| |
| #define | SCB_ABFSR_AXIM_Pos 3U |
| |
| #define | SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) |
| |
| #define | SCB_ABFSR_AHBP_Pos 2U |
| |
| #define | SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) |
| |
| #define | SCB_ABFSR_DTCM_Pos 1U |
| |
| #define | SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) |
| |
| #define | SCB_ABFSR_ITCM_Pos 0U |
| |
| #define | SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) |
| |
Type definitions for the System Control Block Registers.